1. Field of the Invention
The present application relates generally to an improved data processing apparatus and method, and more specifically, to an apparatus and method for optimizing the phase interpolation of clock signals.
2. Background and Related Art
High-precision phase interpolators (also referred to as phase rotators) may be utilized for generation and distribution of low-jitter clock signals in modern high-speed applications, such as microprocessors and Gigabit serial communication links. Such phase interpolators may typically be employed in implementations where clock signals are not synchronized and thus misalignment and errors are possible. Also, such phase interpolators may be employed in implementations with synchronized clock signals where linear steps are required to find the optimal sample point and thus non-linear steps could cause errors or misalignment.
One example application of phase interpolators is in modern broadband communications equipment. Such broadband communications may typically be fiber optic in nature with data transmissions via these fiber optic links being serial streams of data that utilize network components such as switches, relays, bridges, etc. In order to process such data, these network components typically have a serialization/de-serialization transceiver whose transmitter converts parallel data into serial data and whose receiver receives serial data and converts it back into parallel data. Because the clock signals of the transceivers of the various components are not synchronized, phase misalignment is possible and, thus, errors in the sampling of data at the receiver may be encountered.
Referring to FIG. 1A, as known in the art, a phase interpolators 100 is generally used to generate clock signal phase steps having a finer resolution for providing accurate timing control in high-speed serial links. As such, phases generated from a multi-phase PLL or delayline 102 may be further interpolated by a phase rotator 104 in order to provide additional (or finer) phase steps, which may then be used to optimize sampling timing. For example, a sampling clock may include an optimized phase when its sampling edge (e.g., clock's rising edge) is substantially aligned with the center of each bit-period associated with the data stream being sampled. Thus, in order to achieve such an alignment, providing phase tuning with sufficient granularity or resolution may be advantageous. One exemplary application for the use of such a phase rotator may be in DDR (Double Data Rate) memory links, whereby memory reads and writes are facilitated as a result of the generation of finer phases for both address and data clocks. VCO or delayline 102 may, for example, generate clock signals of the same frequency having sixteen (16) different phase steps separated by 22.5 degree increments. The phase rotator 104 may then, for example, generate additional finer phase steps by further dividing the separated 22.5 degree phase increments into an additional eight (8) phases separated by approximately 2.8125 degree increments. Thus a total of one hundred and twenty eight (128) clock phases each having a 2.8125 degree separation are generated.
Referring to FIG. 1B, as known in the art, phase rotator 104 (FIG. 1A) may typically include of phase selectors 108a, 108b, slew-rate control buffers 110a, 110b with controllable drive strength, weight control buffers 112a, 112b, and a summed output node 114. The phase selectors 108a, 108b may choose two adjacent phases (e.g., clock phases 116, 118) from the VCO or delayline 102 (FIG. 1A) outputs. The slew-rate control buffers 110a, 110b may then generate slow slew-rate signals, such as slow slew-rate signal 120, which are appropriate for phase interpolation. The weight control buffers 112a, 112b control the relative strength of the two phases (e.g., clock phases 116, 118) that are slew-rate adjusted in order to generate phase steps of a finer resolution at the summed output node 114.
For a phase rotator to generate linear phase steps with small Duty Cycle Distortion (DCD), the slew-rate control of the phase interpolator is a significant factor. Referring to FIG. 1C, the impact of signal slew-rate on phase interpolation capabilities is depicted. Excessively fast transition times into the phase interpolator may cause severe Differential Non-Linearity (DNL), where DNL may be defined as the deviation of an actual phase step from the ideal phase step (i.e., DNL of a later phase [e.g., Phase C] with respect to an earlier phase [e.g., Phase A]=[Actual Phase C−Actual Phase A]−[Ideal Phase C−Ideal Phase A]).
Referring to FIG. 1C, as known in the art, when a clock rise and fall transitions are excessively fast, the phase steps near A or B, as defined by 122, become too small and the phase steps in the middle of A and B, as defined by 124, become too large. This depicts the occurrence of a wide DNL (i.e., a wide positive for some steps and a wide negative for some steps). Therefore, an optimally controlled clock signal slew-rate at outputs 109a and 109b reduces DNL, as illustrated by the approximately uniform distribution of phase steps defined by 126. The slew-rate, however, may not be excessively slow since the slew-rate of the clock signals at outputs 109a and 109b should swing from rail-to-rail during a given clock period. Without swinging rail-to-rail, the generated slew-rate controlled clock signal at outputs 109a and 109b may exhibit significant DCD at the output, which in turn degrades clock signal timing quality.
Referring to FIG. 1D, as known in the art, an input clock waveform 128 may be slew-controlled in order generate a waveform 130 that is optimized to minimize both DNL and DCD. Thus, for each given clock frequency, the clock signal should be sufficiently slow to establish a phase overlap with an adjacent signal (i.e., DNL reduction), while still having a sufficient rise-fall time for a balanced rail-to-rail swing (i.e., DCD reduction). One challenge associated with using open-loop slew-rate control when implementing a phase rotator is that it may be difficult to achieve both satisfactory DNL and DCD over process-voltage-temperature (PVT) corners of a device. For example, an excessively slow waveform 132, not establishing a full rail-to-rail swing, may lead to an increase in DCD, while an excessively fast waveform 134 may accordingly cause an increase in DNL. At the fastest corner, the slew-rate controlled signal should be sufficiently slow to achieve good DNL. On the other hand, the signal should also swing rail-to-rail at the slowest corner to avoid severe DCD problem.
It may, therefore, be advantageous, among other things, to provide a phase rotator capable of minimizing both DNL and DCD over PVT corners based on a closed-loop slew-rate control architecture for optimizing slew-rate over various clock frequencies.